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MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Octal 3-State Inverting Buffer/ Line Driver/Line Receiver with LSTTL-Compatible Inputs
High-Performance Silicon-Gate CMOS
The MC74HCT240A is identical in pinout to the LS240. This device may be used as a level converter for interfacing TTL or NMOS outputs to High-Speed CMOS inputs. The HCT240A is an octal inverting buffer line driver line receiver designed to be used with 3-state memory address drivers, clock drivers, and other bus-oriented systems. The device has inverting outputs and two active-low output enables. The HCT240A is the inverting version of the HCT244. See also HCT241. * * * * * * Output Drive Capability: 15 LSTTL Loads TTL NMOS-Compatible Input Levels Outputs Directly Interface to CMOS, NMOS, and TTL Operating Voltage Range: 4.5 to 5.5 V Low Input Current: 1 A In Compliance with the Requirements Defined by JEDEC Standard No. 7A * Chip Complexity: 110 FETs or 27.5 Equivalent Gates
MC74HCT240A
N SUFFIX PLASTIC PACKAGE CASE 738-03
1 20 1
20
DW SUFFIX SOIC PACKAGE CASE 751D-04 SD SUFFIX SSOP PACKAGE CASE 940C-03 DT SUFFIX TSSOP PACKAGE CASE 948E-02
20 1
20 1
ORDERING INFORMATION MC74HCTXXXAN MC74HCTXXXADW MC74HCTXXXASD MC74HCTXXXADT Plastic SOIC SSOP TSSOP
LOGIC DIAGRAM
A1 A2 A3 A4 DATA INPUTS B1 B2 B3 B4 2 4 6 8 11 13 15 17 18 16 14 12 9 7 5 3 YA1 YA2 YA3 YA4 YB1 YB2 YB3 YB4 INVERTING OUTPUTS
PIN ASSIGNMENT
ENABLE A A1 YB4 A2 YB3 A3 YB2 A4 YB1 GND 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 VCC ENABLE B YA1 B4 YA2 B3 YA3 B2 YA4 B1
FUNCTION TABLE
OUTPUT ENABLES 1 ENABLE A 19 ENABLE B PIN 20 = VCC PIN 10 = GND Inputs Enable A, Enable B L L H A, B L H X Outputs YA, YB H L Z
Z = High Impedance X = Don't Care
2/97
(c) Motorola, Inc. 1997
1
REV 7
MC74HCT240A
II I II I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I I I I I I II I I I II I I II I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III I I I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I II I II I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I I III I I I I I I II I I I II I I I II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I I I I I I II I I I II I I II I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II IIIIIIIII IIIIIIIIIIII I I II I I I II I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I III I I I II I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I IIIIIIIIIII I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II IIIIIIIIIIIIIIIIIIIIIII III I I IIIIIIIIIIIIIIIIIIIIIII III I III I I II I IIIIIIIIIIIIIIIIIIIIIII III I IIIIIIIIIIIIIIIIIIIIIII III I IIIIIIIIIIIIIIIIIIIIIII III I IIIIIIIIIIIIIIIIIIIIIII III I IIIIIIIIIIIIIIIIIIIIIII III I I IIIIIIIIIIIIIIIIIIIIIII III II I IIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIII I I
IIIIIIII I I II I IIIIIIIIIIIIIIII II I I I IIIIIIIIIIIIIIIIIIIIII I I III I I I I I II IIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII I III I I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII IIIIII I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIII I IIIIIIIIIIIIIIIIIIIIIII
MAXIMUM RATINGS*
Symbol VCC Vin Parameter Value Unit V V V DC Supply Voltage (Referenced to GND) DC Input Voltage (Referenced to GND) - 0.5 to + 7.0 - 0.5 to VCC + 0.5 - 0.5 to VCC + 0.5 20 35 75 750 500 450 Vout Iin DC Output Voltage (Referenced to GND) DC Input Current, per Pin mA mA mA Iout DC Output Current, per Pin ICC PD DC Supply Current, VCC and GND Pins Power Dissipation in Still Air Plastic DIP SOIC Package TSSOP or SSOP Package mW Tstg TL Storage Temperature - 65 to + 150 260
This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance circuit. For proper operation, Vin and Vout should be constrained to the range GND (Vin or Vout) VCC. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or VCC). Unused outputs must be left open.
v
v
_C _C
Lead Temperature, 1 mm from Case for 10 Seconds (Plastic DIP, SOIC, TSSOP or SSOP Package)
* Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the Recommended Operating Conditions. Derating -- Plastic DIP: - 10 mW/_C from 65_ to 125_C SOIC Package: - 7 mW/_C from 65_ to 125_C TSSOP or SSOP Package: - 6.1 mW/_C from 65_ to 125_C For high frequency or heavy load considerations, see Chapter 2 of the Motorola High-Speed CMOS Data Book (DL129/D).
RECOMMENDED OPERATING CONDITIONS
Symbol VCC Parameter Min 4.5 0 Max 5.5 Unit V V
DC Supply Voltage (Referenced to GND)
Vin, Vout TA
DC Input Voltage, Output Voltage (Referenced to GND) Operating Temperature, All Package Types Input Rise and Fall Time (Figure 1)
VCC
- 55 0
+ 125 500
_C
ns
tr, tf
DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)
Guaranteed Limit
Symbol S bl VIH VIL
Parameter P
Test C di i T Conditions
VCC V 4.5 5.5 4.5 5.5 4.5 5.5 4.5 4.5 5.5 4.5 5.5 5.5
- 55 to 25_C 2 2
v 85_C v 125_C
2 2 2 2 0.8 0.8 4.4 5.4 0.8 0.8 44 5.4 3.7 0.1 0.1 0.4
Unit Ui V V V
Minimum High-Level Input Voltage
Vout = 0.1 V or VCC - 0.1 V |Iout| 20 A
v v v v v v
Maximum Low-Level Input Voltage
Vout = 0.1 V or VCC - 0.1 V |Iout| 20 A Vin = VIH or VIL |Iout| 20 A Vin = VIH or VIL |Iout| 6 mA Vin = VIH or VIL |Iout| 20 A Vin = VIH or VIL |Iout| 6 mA
0.8 0.8 4.4 5.4
VOH
Minimum High-Level Output Voltage
3.98 0.1 0.1
3.84 0.1 0.1
VOL
Maximum Low-Level Output Voltage
V
0.26
0.33
Iin
Maximum Input Leakage Current Maximum Three State Leakage Current
Vin = VCC or GND
0.1 0.5
1.0 5.0
1.0 10
A A
IOZ
Output in High-Impedance State Vin = VIL or VIH Vout = VCC or GND
MOTOROLA
2
High-Speed CMOS Logic Data DL129 -- Rev 6
MC74HCT240A
DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)
IIIIIIIIIIIIIIIIIIIIII I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIII I II I I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIII IIIIIIIIIIIIIIIIIIIIIII I I II I I I II I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III I III I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I IIIIIIIIIII I I I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIII I I I
Guaranteed Limit Symbol S bl ICC Parameter P Test C di i T Conditions VCC V 5.5 - 55 to 25_C 4
v 85_C v 125_C
40 160 25_C to 125_C 2.4
Unit Ui A
Maximum Quiescent Supply Current (per Package)
Vin = VCC or GND Iout = 0 A
ICC
Additional Quiescent Supply Current
Vin = 2.4 V, Any One Input Vin = VCC or GND, Other Inputs lout = 0 A
-55_C 2.9
5.5 55
mA A
NOTES: 1. Information on typical parametric values along with frequency or heavy load considerations can be found in Chapter 2 of the Motorola High- Speed CMOS Data Book (DL129/D). 2. Total Supply Current = ICC + ICC.
AC ELECTRICAL CHARACTERISTICS (VCC = 5.0 V 10%, CL = 50 pF, Input tr = tf = 6 ns)
II I I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIII I III I I I IIII I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I I I IIII IIII III I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I III I I I IIII IIII I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III I I I IIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIII I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIII I
Guaranteed Limit Symbol S bl tPLH, tPHL tPLZ, tPHZ tPZL, tPZH Parameter P - 55 to 25_C 20 28 25 12 10 15
v 85_C
25 35 31 15 10 15
v 125_C
30 42 38 18 10 15
Unit Ui ns ns ns ns
Maximum Propagation Delay, A to YA or B to YB (Figures 1 and 3)
Maximum Propagation Delay, Output Enable to YA or YB (Figures 2 and 4) Maximum Propagation Delay, Output Enable to YA or YB (Figures 2 and 4) Maximum Output Transition Time, Any Output (Figures 1 and 3) Maximum Input Capacitance
tTLH, tTHL Cin
pF pF
Cout
Maximum Three-State Output Capacitance (Output in High-Impedance State)
NOTE: For propagation delays with loads other than 50 pF, and information on typical parametric values, see Chapter 2 of the Motorola High- Speed CMOS Data Book (DL129/D). Typical @ 25C, VCC = 5.0 V 55
CPD
Power Di i i C P Dissipation Capacitance (P E bl d O i (Per Enabled Output)* )*
pF F
* Used to determine the no-load dynamic power consumption: P D = C PD V CC 2 f + I CC V CC . For load considerations, see Chapter 2 of the Motorola High-Speed CMOS Data Book (DL129/D).
High-Speed CMOS Logic Data DL129 -- Rev 6
3
MOTOROLA
MC74HCT240A
SWITCHING WAVEFORMS
3V tr INPUT A OR B tPHL OUTPUT YA OR YB tTHL 90% 1.3 V 10% OUTPUT Y tTLH 2.7 V 1.3 V 0.3 V tPLH tf 3V GND OUTPUT Y 1.3 V tPZH 1.3 V tPHZ 10% 90% ENABLE A OR B 1.3 V GND tPZL tPLZ HIGH IMPEDANCE VOL VOH HIGH IMPEDANCE
Figure 1.
Figure 2.
TEST POINT OUTPUT DEVICE UNDER TEST DEVICE UNDER TEST
TEST POINT OUTPUT 1 k CONNECT TO VCC WHEN TESTING tPLZ AND tPZL. CONNECT TO GND WHEN TESTING tPHZ AND tPZH.
CL*
CL*
* Includes all probe and jig capacitance
* Includes all probe and jig capacitance
Figure 3. Test Circuit
Figure 4. Test Circuit
LOGIC DETAIL
TO THREE OTHER A OR B INVERTERS
ONE OF 8 INVERTERS VCC INPUT A OR B YA OR YB
OUTPUT ENABLES ENABLE A OR ENABLE B
MOTOROLA
4
High-Speed CMOS Logic Data DL129 -- Rev 6
MC74HCT240A
OUTLINE DIMENSIONS
N SUFFIX PLASTIC PACKAGE CASE 738-03 ISSUE E
11 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEAD WHEN FORMED PARALLEL. 4. DIMENSION B DOES NOT INCLUDE MOLD FLASH. INCHES MIN MAX 1.010 1.070 0.240 0.260 0.150 0.180 0.015 0.022 0.050 BSC 0.050 0.070 0.100 BSC 0.008 0.015 0.110 0.140 0.300 BSC 0_ 15 _ 0.020 0.040 MILLIMETERS MIN MAX 25.66 27.17 6.10 6.60 3.81 4.57 0.39 0.55 1.27 BSC 1.27 1.77 2.54 BSC 0.21 0.38 2.80 3.55 7.62 BSC 0_ 15_ 0.51 1.01
-A-
20
B
1 10
C
L
-T-
SEATING PLANE
K M E G F D
20 PL
N J 0.25 (0.010)
M 20 PL
0.25 (0.010) TA
M
M
TB
M
DIM A B C D E F G J K L M N
-A-
20 11
DW SUFFIX PLASTIC SOIC PACKAGE CASE 751D-04 ISSUE E
-B-
1 10
10X
P 0.010 (0.25)
M
B
M
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.150 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.13 (0.005) TOTAL IN EXCESS OF D DIMENSION AT MAXIMUM MATERIAL CONDITION. DIM A B C D F G J K M P R MILLIMETERS MIN MAX 12.65 12.95 7.40 7.60 2.35 2.65 0.35 0.49 0.50 0.90 1.27 BSC 0.25 0.32 0.10 0.25 0_ 7_ 10.05 10.55 0.25 0.75 INCHES MIN MAX 0.499 0.510 0.292 0.299 0.093 0.104 0.014 0.019 0.020 0.035 0.050 BSC 0.010 0.012 0.004 0.009 0_ 7_ 0.395 0.415 0.010 0.029
20X
D
M
0.010 (0.25)
TA
S
B
J
S
F R X 45 _ C -T-
18X SEATING PLANE
G
K
M
High-Speed CMOS Logic Data DL129 -- Rev 6
5
MOTOROLA
MC74HCT240A
OUTLINE DIMENSIONS
SD SUFFIX PLASTIC SSOP PACKAGE CASE 940C-03 ISSUE B
20X
K REF 0.12 (0.005)
M
TU
S
V
0.25 (0.010)
S
N M N
L/2 L
PIN 1 IDENT
20
11
B
1 10
F DETAIL E K J
0.20 (0.008)
M
TU
S
SECTION N-N -W-
0.076 (0.003) -T-
SEATING PLANE
C D G H
DETAIL E
20X
K REF
DT SUFFIX PLASTIC TSSOP PACKAGE CASE 948E-02 ISSUE A
M
0.15 (0.006) T U
S
0.10 (0.004)
TU
S
V
S
2X
L/2
20
11
L
PIN 1 IDENT 1 10
B -U-
J J1
N 0.15 (0.006) T U
S
A -V- N F
C D 0.100 (0.004) -T- SEATING
PLANE
G
H
DETAIL E
MOTOROLA
6
IIII IIII IIII
EEE CCC EEE CCC
K1 K K1 DETAIL E
A -V-
-U-
J1
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 5. DIMENSION K DOES NOT INCLUDE DAMBAR PROTRUSION/INTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.13 (0.005) TOTAL IN EXCESS OF K DIMENSION AT MAXIMUM MATERIAL CONDITION. DAMBAR INTRUSION SHALL NOT REDUCE DIMENSION K BY MORE THAN 0.07 (0.002) AT LEAST MATERIAL CONDITION. 6. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 7. DIMENSION A AND B ARE TO BE DETERMINED AT DATUM PLANE -W-. DIM A B C D F G H J J1 K K1 L M MILLIMETERS MIN MAX 7.07 7.33 5.20 5.38 1.73 1.99 0.05 0.21 0.63 0.95 0.65 BSC 0.59 0.75 0.09 0.20 0.09 0.16 0.25 0.38 0.25 0.33 7.65 7.90 0_ 8_ INCHES MIN MAX 0.278 0.288 0.205 0.212 0.068 0.078 0.002 0.008 0.024 0.037 0.026 BSC 0.023 0.030 0.003 0.008 0.003 0.006 0.010 0.015 0.010 0.013 0.301 0.311 0_ 8_
SECTION N-N
0.25 (0.010)
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 (0.010) PER SIDE. 5. DIMENSION K DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE K DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 7. DIMENSION A AND B ARE TO BE DETERMINED AT DATUM PLANE -W-. MILLIMETERS MIN MAX 6.40 6.60 4.30 4.50 --- 1.20 0.05 0.15 0.50 0.75 0.65 BSC 0.27 0.37 0.09 0.20 0.09 0.16 0.19 0.30 0.19 0.25 6.40 BSC 0_ 8_ INCHES MIN MAX 0.252 0.260 0.169 0.177 --- 0.047 0.002 0.006 0.020 0.030 0.026 BSC 0.011 0.015 0.004 0.008 0.004 0.006 0.007 0.012 0.007 0.010 0.252 BSC 0_ 8_
M
DIM A B C D F G H J J1 K K1 L M
-W-
High-Speed CMOS Logic Data DL129 -- Rev 6
MC74HCT240A
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High-Speed CMOS Logic Data DL129 -- Rev 6
7
MC74HCT240A/D MOTOROLA

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